1. Field of the Invention
The present invention relates to semiconductor memory devices, more specifically, to an EEPROM including a selection transistor, and a method of fabricating the same.
2. Description of the Related Art
Electrically erasable and programmable read only memory (EEPROM) is a memory device for electrically memorizing and erasing data and includes a flash memory device and a FLOTOX memory device representatively. The FLOTOX memory device includes a memory cell composed of two transistors (i.e., a memory transistor and a selection transistor). In contrast, the flash memory device includes a memory cell composed of one transistor. A cell array of the flash memory devices is categorized as a NAND type and a NOR type according to the arrangement of memory cells. Cell strings are disposed parallel in the NAND type cell array and are composed of a plurality of memory cells that are connected to each other in series. The cell string of a NAND type cell array includes selection transistors at both edges thereof similar to a FLOTOX memory device. However, the selection transistor of a NAND type flash memory device selects a cell string whereas the selection transistor of a FLOTOX memory device selects a memory cell.
An insulation layer is interposed between a lower conductive layer and an upper conductive layer in a stacked formation in the transistors of an EEPROM cell. The upper conductive layer and the lower conductive layer of the memory cell should be electrically insulated from each other in order to store data. However, the lower conductive layer of the selection transistor should be electrically connected to the upper conductive layer thereof. Therefore, various structures for connecting the lower conductive layer to the upper conductive layer in the selection transistor have been proposed. EEPROM memory devices including a selection transistor are disclosed in U.S. Pat. Nos. 4,780,431 and 6,221,717.
FIG. 1 is a top plan view illustrating a portion of cell arrays of a conventional NAND type flash memory device.
Referring to FIG. 1, a device isolation layer 2 is disposed in a semiconductor substrate to dispose a plurality of active regions 4. A string selection line SSL, a ground selection line GSL and a plurality of word lines WL are placed to extend across the active regions 4. A memory cell unit is composed of the string selection line SSL, the ground selection line GSL and the plurality of word lines WL therebetween. The NAND type cell array comprises a plurality of memory cell units in symmetrically repeated arrangement. A common source line CSL is disposed between the neighboring ground selection lines GSL for electrically connecting the active regions 4, and a bit line plug 44 that is disposed on each of the active region 4 between the neighboring string selection lines SSL.
The word line WL includes a control gate pattern 49 extending across the active regions 4 and a floating gate 34 formed on each of the active regions 4. The ground selection line GSL and the string selection line SSL include a lower gate pattern 24 and a selection gate pattern 30 in a sequentially stacked form. Contrary to this, the selection gate pattern 30 should be electrically connected to the lower gate pattern 24. Conventionally, the selection gate pattern 30 is connected to lower gate pattern 24 by a butting contact or by removing a portion of the inter-gate dielectric layer formed between the selection gate pattern 30 and the lower gate pattern 24.
FIGS. 2 and 3 are cross-sectional views taken along line I-I′ of FIG. 1 illustrating a method for forming a conventional EEPROM.
Referring to FIG. 2, a gate insulation layer and a first conductive layer are formed on the semiconductor substrate 10. Then, the first conductive layer is patterned to form a first conductive pattern 14. An inter-gate dielectric layer 16 and a mask conductive layer 18 are sequentially formed on the semiconductor substrate including the first conductive pattern 14. The mask conductive layer 18 and the inter-gate dielectric layer 16 are successively patterned to form an opening 20 exposing the first conductive pattern 14. As not illustrated in the drawings, the opening 20 extends across the active regions 2. The opening 20 may be formed on the center of region S where the selection line is formed.
Referring to FIG. 3, a second conductive layer is formed on the mask conductive layer 18 with the opening 20. The second conductive layer, the mask conductive layer 18, the inter-gate dielectric layer 16a and the first conductive pattern 14 are successively patterned to form a word line WL and the selection line SL. The word line WL includes a floating gate 34, an inter-gate dielectric pattern 36, a mask conductive pattern 38 and a control gate pattern 40 in a sequentially stacked form. The selection line SL includes a lower gate pattern 24, a dummy dielectric pattern 26, a mask conductive pattern 28 and a selection gate pattern 30. The floating gate pattern 34 and the control gate pattern 40 are electrically insulated from each other but the lower gate pattern 24 and the selection gate pattern 30 are electrically connected through the opening 20. The opening 20 may be formed to have a width of, for example, half a line width L of the selection line SL. In this case, a misalignment tolerance of the opening 20 and the selection line SL is L/4.
FIGS. 4 and 5 are cross-sectional views illustrating problems of the prior art.
Referring to FIG. 4, if the opening 20 or the selection line SL is misaligned, a portion 46 of the opening 20 misses the selection line region S.
Referring to FIG. 5, the second conductive layer is formed, and the second conductive layer and the mask conductive layer are patterned using the inter-gate dielectric layer 16 as an etch stop layer to form a control gate pattern 40, a selection gate pattern 30 and mask conductive patterns 28 and 38. In this case, the first conductive pattern 14 missing the selection line region S is removed from the opening region 46 to expose the gate insulation layer 12.
Referring to FIG. 6, the inter-gate dielectric layer 16 and the first conductive pattern 14 are patterned to form a floating gate 34, a lower gate pattern 24 and an inter-gate dielectric pattern 36 and a dummy dielectric pattern 26. In this case, the semiconductor substrate in the opening region 20 may be damaged by the etching. For example, a notch 48 can be formed adjacent the selection line SL.